frequency.h

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#ifndef STC15_FREQH
#define STC15_FREQH
 
#include <sys.h>
#include <bits.h>
 
#define CLK_DIV_MASK 0x07
 
#define get_master_clock_frequency() (MAIN_Fosc)
 
#define get_master_clock_frequency_high_part() (MAIN_FoscH)
 
#define get_master_clock_frequency_low_part() (MAIN_FoscL)
 
#define get_frequency_divider() (1 << get_frequency_divider_scale())
 
#define get_frequency_divider_scale() (CLK_DIV & CLK_DIV_MASK)
 
#define set_frequency_divider_scale(divider_scale)      \
do {                                                    \
    CLK_DIV &= 0xf8;                                    \
    CLK_DIV |= (divider_scale & CLK_DIV_MASK);          \
} while(0)
 
 
#define SYSclk (get_master_clock_frequency() >> get_frequency_divider_scale())
 
#define enable_master_clock_output_div1() (CLK_DIV |= 0x40)
 
#define enable_master_clock_output_div2() (CLK_DIV |= 0x80)
 
#define enable_master_clock_output_div4() (CLK_DIV |= 0xC0)
 
#define disable_master_clock_output() (CLK_DIV &= 0x3f)
 
typedef enum 
{
    NONE, 
    P5_4, 
    P1_6  
} master_clock_output_pin_t;
 
#define get_master_clock_output_pin() ((CLK_DIV & 0xC0) == 0 ? NONE : (CLK_DIV & 0x08) == 0 ? P5_4 : P1_6)
 
#pragma save
#pragma disable_warning 126
#define set_master_clock_output_pin(pin)            \
do {                                                \
    if (pin == NONE)                                \
    {                                               \
        disable_master_clock_output();              \
    }                                               \
    else if (pin == P5_4)                           \
    {                                               \
        bit_clr(CLK_DIV, SBIT3);                    \
    }                                               \
    else if (pin == P1_6)                           \
    {                                               \
        bit_set(CLK_DIV, SBIT3);                    \
    }                                               \
} while(0)
#pragma restore
 
#endif