Macros
#define	get_master_clock_frequency() (MAIN_Fosc)
	Get MAIN_Fosc value. More...

#define	get_master_clock_frequency_high_part() (MAIN_FoscH)
	Get high part of MAIN_Fosc defined as MAIN_FoscH in sys.h. More...

#define	get_master_clock_frequency_low_part() (MAIN_FoscL)
	Get low part of MAIN_Fosc defined as MAIN_FoscL in sys.h. More...

#define	get_frequency_divider() (1 << (CLK_DIV & 0x07))
	Get master clock frequency divider (1 << CLK_DIV bits [0..2]) More...

#define	get_frequency_divider_scale() (CLK_DIV & 0x07)
	Get master clock frequency divider scale (CLK_DIV bits [0..2]) More...

#define	set_frequency_divider_scale(divider_scale)
	Update and get master clock frequency divider (CLK_DIV bits [0..2]) More...

#define	enable_master_clock_output_div1() (CLK_DIV \|= 0x40)
	Enable master clock output. By default output set to P5.4 pin. More...

#define	enable_master_clock_output_div2() (CLK_DIV \|= 0x80)
	Enable (master clock output)/2. By default output set to P5.4 pin. More...

#define	enable_master_clock_output_div4() (CLK_DIV \|= 0xC0)
	Enable (master clock output)/4. By default output set to P5.4 pin. More...

#define	disable_master_clock_output() (CLK_DIV &= 0x3f)
	Disable master clock output. More...

#define	get_master_clock_output_pin() ((CLK_DIV & 0xC0) == 0 ? NONE : (CLK_DIV & 0x08) == 0 ? P5_4 : P1_6)
	Get master clock output. More...

#define	set_master_clock_output_pin(pin)
	Set master clock output pin. More...

Enumerations
enum	master_clock_output_pin_t { NONE , P5_4 , P1_6 }
	Master clock output pins enumeration. More...

Detailed Description

Functions and data structures for get chip CPU frequency. Chip CPU frequency defined in sys.h as a MAIN_Fosc constant.

Author: Michael Golovanov

Macro Definition Documentation

◆ disable_master_clock_output

#define disable_master_clock_output ( ) (CLK_DIV &= 0x3f)

Disable master clock output.

See also: enable_master_clock_output_div1(); enable_master_clock_output_div2(); enable_master_clock_output_div4()

◆ enable_master_clock_output_div1

#define enable_master_clock_output_div1 ( ) (CLK_DIV |= 0x40)

Enable master clock output. By default output set to P5.4 pin.

See also: disable_master_clock_output(); set_master_clock_output_pin(master_clock_output_pin pin)

◆ enable_master_clock_output_div2

#define enable_master_clock_output_div2 ( ) (CLK_DIV |= 0x80)

Enable (master clock output)/2. By default output set to P5.4 pin.

See also: disable_master_clock_output(); set_master_clock_output_pin(master_clock_output_pin pin)

◆ enable_master_clock_output_div4

#define enable_master_clock_output_div4 ( ) (CLK_DIV |= 0xC0)

Enable (master clock output)/4. By default output set to P5.4 pin.

See also: disable_master_clock_output(); set_master_clock_output_pin(master_clock_output_pin pin)

◆ get_frequency_divider

#define get_frequency_divider ( ) (1 << (CLK_DIV & 0x07))

Get master clock frequency divider (1 << CLK_DIV bits [0..2])

Returns: master clock frequency divider. Divider values range is from 1 to 128.

See also: get_frequency_divider_scale(uint8_t divider_scale)

◆ get_frequency_divider_scale

#define get_frequency_divider_scale ( ) (CLK_DIV & 0x07)

Get master clock frequency divider scale (CLK_DIV bits [0..2])

Returns: master clock frequency divider scale. Divider scale range is from 0 to 7.

See also: get_frequency_divider_scale(uint8_t divider_scale)

◆ get_master_clock_frequency

#define get_master_clock_frequency ( ) (MAIN_Fosc)

Get MAIN_Fosc value.

Returns: MAIN_Fosc value

◆ get_master_clock_frequency_high_part

#define get_master_clock_frequency_high_part ( ) (MAIN_FoscH)

Get high part of MAIN_Fosc defined as MAIN_FoscH in sys.h.

Returns: MAIN_FoscH

◆ get_master_clock_frequency_low_part

#define get_master_clock_frequency_low_part ( ) (MAIN_FoscL)

Get low part of MAIN_Fosc defined as MAIN_FoscL in sys.h.

Returns: MAIN_FoscL

◆ get_master_clock_output_pin

#define get_master_clock_output_pin ( ) ((CLK_DIV & 0xC0) == 0 ? NONE : (CLK_DIV & 0x08) == 0 ? P5_4 : P1_6)

Get master clock output.

Returns: info about current master clock output

◆ set_frequency_divider_scale

#define set_frequency_divider_scale ( divider_scale )

Value:

{                                                       \
    CLK_DIV &= 0xf8;                                    \
    CLK_DIV |= (divider_scale & 0x07);                  \
}

Update and get master clock frequency divider (CLK_DIV bits [0..2])

Before setting divider value validate if divider scale is out of range 0..7.

Parameters

divider_scale uint8 scale from 0 to 7 corresponds dividers 1, 2, 4, ...128

Returns: master clock frequency divider value

See also: get_frequency_divider()

◆ set_master_clock_output_pin

#define set_master_clock_output_pin ( pin )