Macros
#define	CLK_DIV_MASK 0x07
	MCU frequency divider bitmask (3 low bits of CLK_DIV registry)

#define	get_master_clock_frequency() (MAIN_Fosc)
	Get MAIN_Fosc value.

#define	get_master_clock_frequency_high_part() (MAIN_FoscH)
	Get high part of MAIN_Fosc defined as MAIN_FoscH in sys.h.

#define	get_master_clock_frequency_low_part() (MAIN_FoscL)
	Get low part of MAIN_Fosc defined as MAIN_FoscL in sys.h.

#define	get_frequency_divider() (1 << get_frequency_divider_scale())
	Get master clock frequency divider (1 << CLK_DIV bits [0..2])

#define	get_frequency_divider_scale() (CLK_DIV & CLK_DIV_MASK)
	Get master clock frequency divider scale (CLK_DIV bits [0..2])

#define	set_frequency_divider_scale(divider_scale)
	Update and get master clock frequency divider (CLK_DIV bits [0..2])

#define	SYSclk (get_master_clock_frequency() >> get_frequency_divider_scale())
	System clock frequency.

#define	enable_master_clock_output_div1() (CLK_DIV \|= 0x40)
	Enable master clock output. By default output set to P5.4 pin.

#define	enable_master_clock_output_div2() (CLK_DIV \|= 0x80)
	Enable (master clock output)/2. By default output set to P5.4 pin.

#define	enable_master_clock_output_div4() (CLK_DIV \|= 0xC0)
	Enable (master clock output)/4. By default output set to P5.4 pin.

#define	disable_master_clock_output() (CLK_DIV &= 0x3f)
	Disable master clock output.

#define	get_master_clock_output_pin() ((CLK_DIV & 0xC0) == 0 ? NONE : (CLK_DIV & 0x08) == 0 ? P5_4 : P1_6)
	Get master clock output.

#define	set_master_clock_output_pin(pin)
	Set master clock output pin.

Enumerations
enum	master_clock_output_pin_t { NONE , P5_4 , P1_6 }
	Master clock output pins enumeration. More...

Detailed Description

Functions and data structures for get chip CPU frequency. Chip CPU frequency defined in sys.h as a MAIN_Fosc constant.

Author: Michael Golovanov

Macro Definition Documentation

◆ disable_master_clock_output

#define disable_master_clock_output ( ) (CLK_DIV &= 0x3f)

Disable master clock output.

See also: enable_master_clock_output_div1(); enable_master_clock_output_div2(); enable_master_clock_output_div4()

◆ enable_master_clock_output_div1

#define enable_master_clock_output_div1 ( ) (CLK_DIV |= 0x40)

Enable master clock output. By default output set to P5.4 pin.

See also: disable_master_clock_output(); set_master_clock_output_pin(master_clock_output_pin pin)

◆ enable_master_clock_output_div2

#define enable_master_clock_output_div2 ( ) (CLK_DIV |= 0x80)

Enable (master clock output)/2. By default output set to P5.4 pin.

See also: disable_master_clock_output(); set_master_clock_output_pin(master_clock_output_pin pin)

◆ enable_master_clock_output_div4

#define enable_master_clock_output_div4 ( ) (CLK_DIV |= 0xC0)

Enable (master clock output)/4. By default output set to P5.4 pin.

See also: disable_master_clock_output(); set_master_clock_output_pin(master_clock_output_pin pin)

◆ get_frequency_divider

#define get_frequency_divider ( ) (1 << get_frequency_divider_scale())

Get master clock frequency divider (1 << CLK_DIV bits [0..2])

Returns: master clock frequency divider. Divider values range is from 1 to 128.

See also: get_frequency_divider_scale(uint8_t divider_scale)

◆ get_frequency_divider_scale

#define get_frequency_divider_scale ( ) (CLK_DIV & CLK_DIV_MASK)

Get master clock frequency divider scale (CLK_DIV bits [0..2])

Returns: master clock frequency divider scale. Divider scale range is from 0 to 7.

See also: get_frequency_divider_scale(uint8_t divider_scale)

◆ get_master_clock_frequency

#define get_master_clock_frequency ( ) (MAIN_Fosc)

Get MAIN_Fosc value.

Returns: MAIN_Fosc value

◆ get_master_clock_frequency_high_part

#define get_master_clock_frequency_high_part ( ) (MAIN_FoscH)

Get high part of MAIN_Fosc defined as MAIN_FoscH in sys.h.

Returns: MAIN_FoscH

◆ get_master_clock_frequency_low_part

#define get_master_clock_frequency_low_part ( ) (MAIN_FoscL)

Get low part of MAIN_Fosc defined as MAIN_FoscL in sys.h.

Returns: MAIN_FoscL

◆ get_master_clock_output_pin

#define get_master_clock_output_pin ( ) ((CLK_DIV & 0xC0) == 0 ? NONE : (CLK_DIV & 0x08) == 0 ? P5_4 : P1_6)

Get master clock output.

Returns: info about current master clock output

◆ set_frequency_divider_scale

#define set_frequency_divider_scale ( divider_scale )

Value:

do {                                                    \
    CLK_DIV &= 0xf8;                                    \
    CLK_DIV |= (divider_scale & CLK_DIV_MASK);          \
} while(0)

Update and get master clock frequency divider (CLK_DIV bits [0..2])

Before setting divider value validate if divider scale is out of range 0..7.

Parameters

divider_scale uint8 scale from 0 to 7 corresponds dividers 1, 2, 4, ...128

Returns: master clock frequency divider value

See also: get_frequency_divider()

◆ set_master_clock_output_pin

#define set_master_clock_output_pin ( pin )

Value:

do {                                                \
    if (pin == NONE)                                \
    {                                               \
        disable_master_clock_output();              \
    }                                               \
    else if (pin == P5_4)                           \
    {                                               \
        bit_clr(CLK_DIV, CBIT3);                    \
    }                                               \
    else if (pin == P1_6)                           \
    {                                               \
        bit_set(CLK_DIV, SBIT3);                    \
    }                                               \
} while(0)

Set master clock output pin.

Parameters

pin	master_clock_output_pin_t pin to set output

◆ SYSclk

#define SYSclk (get_master_clock_frequency() >> get_frequency_divider_scale())

System clock frequency.

This routine calculates the actual system clock frequency that the CPU is running at, taking into account the main oscillator frequency and the clock divider setting.

The formula is: SYSclk = MAIN_Fosc / (2^divider_scale) where:

MAIN_Fosc is the main oscillator frequency defined in sys.h
divider_scale is the value in bits [0..2] of the CLK_DIV register

This represents the effective CPU clock frequency after any prescaling has been applied. For example, if MAIN_Fosc is 11,059,200 Hz and the divider_scale is 1 (dividing by 2), then SYSclk would be 5,529,600 Hz.

See also: get_master_clock_frequency() - function that returns the main oscillator frequency; get_frequency_divider_scale() - function that returns the current clock divider scale; set_frequency_divider_scale() - function to change the clock divider

Enumeration Type Documentation

◆ master_clock_output_pin_t

enum master_clock_output_pin_t

Master clock output pins enumeration.

Enumerator
NONE	output disabled
P5_4	output to pin 5.4
P1_6	output to pin 1.6

Macros

Enumerations