Timer configuration reading

Enumerations
enum	timer_clock_divider_t { T1 = 1 , T12 = 12 }
	Timer clock divider values enum. More...

Timer0
Timer0 routines
#define	get_timer0_mode()   (TMOD & 0x03)
	Get mode for timer0.
#define	get_timer0_clock_divider()   (test_if_bit_cleared(AUXR, SBIT7) ? T12 : T1)
	Get clock divider for timer0.

Timer2
Timer2 routines
#define	get_timer2_mode()   (0)
	Get mode for timer2.
#define	get_timer2_clock_divider()   (test_if_bit_set(AUXR, SBIT2) ? T1 : T12)
	Get clock divider for timer2.

Detailed Description

This module contains reading mode and divider from configured timer or counter routines

Author

Michael Golovanov

Macro Definition Documentation

get_timer0_clock_divider

#define get_timer0_clock_divider

(

)

(test_if_bit_cleared(AUXR, SBIT7) ? T12 : T1)

Get clock divider for timer0.

Returns

timer0 clock divider

get_timer0_mode

#define get_timer0_mode

(

)

(TMOD & 0x03)

Get mode for timer0.

Returns

timer0 mode in range from 0 to 3

get_timer2_clock_divider

#define get_timer2_clock_divider

(

)

(test_if_bit_set(AUXR, SBIT2) ? T1 : T12)

Get clock divider for timer2.

Returns

timer2 clock divider

get_timer2_mode

#define get_timer2_mode

(

)

(0)

Get mode for timer2.

Returns

timer2 mode. Timer2 have only mode0.

Enumeration Type Documentation

timer_clock_divider_t

enum timer_clock_divider_t

Timer clock divider values enum.

Enumerator
T1	Sysclk/1.
T12	Sysclk/12.