add get chip id function (value F51FC47E1D0B52 for STC15W408AS)
add master clock and divider frequency functions
adapt delay_ms to clock divider, uart not adapted yet
0.3.0
add master clock output to pin P5.4 or P1.6 with dividers 1, 2, 4
get mode functions for timer0 and timer2
get clock divider functions for timer0 and timer2
timer0 mode0/12T and mode0/1T implementation with sync and interrupt (async) support. No GATE and INT0 support for timer0 running, only TR0 used for start and stop timer. No P3.5 output.
timer2 mode0/12T and mode0/1T implementation with interrupt (async) support. No P3.0 output.
0.4.0
Enable and disable timer0 mode0 output to P3.5 pin supported now
Enable and disable timer2 mode0 output to P3.0 pin supported now
timer0_enable_on_pinINT0_high implemented for timer0 work only on INT0/P3.0 pin is high
Fix: copy eerprom_data.hex on cmake build eeprom examples
Fix: Cmake firmware size is not equal to PlatformIO build size
Fix: Firmware built by SDCC 4.5 works correctly
Comparator module initial implementation
EEPROM write array implemented
0.16.0
Wakeup timer init for a given duration routine implemented
Timer conversions between ticks and ms/frequency routines refactored
timer0_modeX_delay() simplified
pin examples folder renamed to gpio
Timer0 start on ms/mcs routines implemented
Timer2 mode0 start on ms/mcs routines implemented
Timer0 starts on freq routines implemented
Timer2 mode0 start on freq routines implemented
0.17.0
Timer0 sync delay routines implemented
CMake examples flash_* targets are fixed
Memory dump not only idata but xdata memory too
Memory dumper is documented
CMake and PlatformIO generate a build summary with firmware sizes table
SCons make STC15 library for examples and utilities build
Now CMake build can use SDCC 4.1 (PlatformIO), 4.5 (Default for Debian Trixie), and 4.6 (lastest on a current time sdcc version). 4.5 usedd by default
GitHub build. On the new tag GitHub CI builds release with artifacts and draft release.
0.18.0
Group PlatformIO and CMake build files in separate folders
Separate ./README on parts for firmware dev and contributor parts
Corrected library.json – Fix a license type from MIT to Apache
PCA/CCP module implemented (pca.h): pin group selection, counter clock source, 16 bit counter, compare/capture, high speed toggle output and 8/7/6 bit PWM
PCA examples added to examples/pca (PWM, 16 bit timer and capture)
Host tests for library headers added to test/ and wired to ctest
SPI module implemented (spi.h): master and slave mode, 4 clock dividers, all 4 CPOL/CPHA modes, MSB/LSB first, 3 pin groups, sync and async transfer, write collision detection
SPI example added to examples/spi (master loopback)
Rework bits module.
GitHub CI/CD: add build summary and examples to release
Next releases todo
TODO bits module remove SBIT definitions.
TODO All modules define bit positions, mask and bits
TODO Use static_assert
TODO UART1 support frame error
TODO UART1 Automatic address recognition support
TODO UART1 Relay broadcast mode support
TODO UART1 does not work correctly with freq scaling
TODO is PCON SMOD bit really double baud rate in mode 1, 2, 3?
TODO Try to read/write EEPROM using MOVC assembler command
TODO Timer sync delay implementation could use idle and isr handler