spi.h

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#ifndef STC15_SPIH
#define STC15_SPIH
 
#include <sys.h>
#include <bits.h>
#include <gpio.h>
 
#define SPI_SSIG_BIT 7
#define SPI_SPEN_BIT 6
#define SPI_DORD_BIT 5
#define SPI_MSTR_BIT 4
#define SPI_CPOL_BIT 3
#define SPI_CPHA_BIT 2
#define SPI_SPR1_BIT 1
#define SPI_SPR0_BIT 0
 
#define SPI_SSIG_MSK 0x80
#define SPI_SPEN_MSK 0x40
#define SPI_DORD_MSK 0x20
#define SPI_MSTR_MSK 0x10
#define SPI_CPOL_MSK 0x08
#define SPI_CPHA_MSK 0x04
#define SPI_SPR_MSK 0x03
 
#define SPI_SPIF_BIT 7
#define SPI_WCOL_BIT 6
 
#define SPI_SPIF_MSK 0x80
#define SPI_WCOL_MSK 0x40
#define SPI_SPSTAT_CLEAR_MSK (SPI_SPIF_MSK | SPI_WCOL_MSK)
 
#define SPI_S0_BIT 2
#define SPI_S0_MASK 0x04
#define SPI_S1_MASK 0x08
#define SPI_SW_MASK (SPI_S0_MASK | SPI_S1_MASK)
 
typedef enum
{
    SPI_CLOCK_DIV_4 = 0b00000000,
    SPI_CLOCK_DIV_16 = 0b00000001,
    SPI_CLOCK_DIV_64 = 0b00000010,
    SPI_CLOCK_DIV_128 = 0b00000011
} spi_clock_t;
 
typedef enum
{
    SPI_MODE_0 = 0b00000000,
    SPI_MODE_1 = 0b00000100,
    SPI_MODE_2 = 0b00001000,
    SPI_MODE_3 = 0b00001100
} spi_mode_t;
 
typedef enum
{
    SPI_PIN_GROUP_1 = 0,
    SPI_PIN_GROUP_2 = 1,
    SPI_PIN_GROUP_3 = 2
} spi_pin_group_t;
 
#define spi_init_master_pins_SPI_PIN_GROUP_1()                               \
do {                                                                         \
    /* SS on P1.2 as push-pull output, kept high */                          \
    pin_push_pull_init(P1, 2);                                               \
    bit_set(P1, SBIT2);                                                      \
    /* MOSI on P1.3 as push-pull output */                                   \
    pin_push_pull_init(P1, 3);                                               \
    /* MISO on P1.4 as input only */                                         \
    pin_input_only_init(P1, 4);                                              \
    /* SCLK on P1.5 as push-pull output */                                   \
    pin_push_pull_init(P1, 5);                                               \
} while(0)
 
#define spi_init_master_pins_SPI_PIN_GROUP_2()                               \
do {                                                                         \
    /* SS_2 on P2.4 as push-pull output, kept high */                        \
    pin_push_pull_init(P2, 4);                                               \
    bit_set(P2, SBIT4);                                                      \
    /* MOSI_2 on P2.3 as push-pull output */                                 \
    pin_push_pull_init(P2, 3);                                               \
    /* MISO_2 on P2.2 as input only */                                       \
    pin_input_only_init(P2, 2);                                              \
    /* SCLK_2 on P2.1 as push-pull output */                                 \
    pin_push_pull_init(P2, 1);                                               \
} while(0)
 
#define spi_init_master_pins_SPI_PIN_GROUP_3()                               \
do {                                                                         \
    /* SS_3 on P5.4 as push-pull output, kept high */                        \
    pin_push_pull_init(P5, 4);                                               \
    bit_set(P5, SBIT4);                                                      \
    /* MOSI_3 on P4.0 as push-pull output */                                 \
    pin_push_pull_init(P4, 0);                                               \
    /* MISO_3 on P4.1 as input only */                                       \
    pin_input_only_init(P4, 1);                                              \
    /* SCLK_3 on P4.3 as push-pull output */                                 \
    pin_push_pull_init(P4, 3);                                               \
} while(0)
 
#define spi_init_slave_pins_SPI_PIN_GROUP_1()                                \
do {                                                                         \
    /* SS on P1.2 as input only */                                           \
    pin_input_only_init(P1, 2);                                              \
    /* MOSI on P1.3 as input only */                                         \
    pin_input_only_init(P1, 3);                                              \
    /* MISO on P1.4 as push-pull output */                                   \
    pin_push_pull_init(P1, 4);                                               \
    /* SCLK on P1.5 as input only */                                         \
    pin_input_only_init(P1, 5);                                              \
} while(0)
 
#define spi_init_slave_pins_SPI_PIN_GROUP_2()                                \
do {                                                                         \
    /* SS_2 on P2.4 as input only */                                         \
    pin_input_only_init(P2, 4);                                              \
    /* MOSI_2 on P2.3 as input only */                                       \
    pin_input_only_init(P2, 3);                                              \
    /* MISO_2 on P2.2 as push-pull output */                                 \
    pin_push_pull_init(P2, 2);                                               \
    /* SCLK_2 on P2.1 as input only */                                       \
    pin_input_only_init(P2, 1);                                              \
} while(0)
 
#define spi_init_slave_pins_SPI_PIN_GROUP_3()                                \
do {                                                                         \
    /* SS_3 on P5.4 as input only */                                         \
    pin_input_only_init(P5, 4);                                              \
    /* MOSI_3 on P4.0 as input only */                                       \
    pin_input_only_init(P4, 0);                                              \
    /* MISO_3 on P4.1 as push-pull output */                                 \
    pin_push_pull_init(P4, 1);                                               \
    /* SCLK_3 on P4.3 as input only */                                       \
    pin_input_only_init(P4, 3);                                              \
} while(0)
 
#define spi_ss_clr_SPI_PIN_GROUP_1() (bit_clr(P1, SBIT2))
 
#define spi_ss_set_SPI_PIN_GROUP_1() (bit_set(P1, SBIT2))
 
#define spi_ss_clr_SPI_PIN_GROUP_2() (bit_clr(P2, SBIT4))
 
#define spi_ss_set_SPI_PIN_GROUP_2() (bit_set(P2, SBIT4))
 
#define spi_ss_clr_SPI_PIN_GROUP_3() (bit_clr(P5, SBIT4))
 
#define spi_ss_set_SPI_PIN_GROUP_3() (bit_set(P5, SBIT4))
 
 
#define spi_init_master_pins(group) spi_init_master_pins_##group()
 
#define spi_init_slave_pins(group) spi_init_slave_pins_##group()
 
#define spi_init_master(group, mode, clock, lsb_first)                       \
do {                                                                         \
    /* Select the SS/MOSI/MISO/SCLK pin group */                             \
    spi_set_pin_group(group);                                                \
    /* Configure the SS/MOSI/MISO/SCLK pins */                               \
    spi_init_master_pins(group);                                             \
    /* Enable SPI as a master with the given mode, clock and data order */   \
    SPCTL = SPI_SPEN_MSK | SPI_MSTR_MSK | (mode) | (clock) |                 \
        ((lsb_first) ? SPI_DORD_MSK : 0) |                                   \
        (((mode) & SPI_CPHA_MSK) ? SPI_SSIG_MSK : 0);                        \
} while(0)
 
#define spi_init_slave(group, mode, lsb_first)                               \
do {                                                                         \
    /* Select the SS/MOSI/MISO/SCLK pin group */                             \
    spi_set_pin_group(group);                                                \
    /* Configure the SS/MOSI/MISO/SCLK pins */                               \
    spi_init_slave_pins(group);                                              \
    /* Enable SPI as a slave with the given mode and data order */           \
    SPCTL = SPI_SPEN_MSK | (mode) | ((lsb_first) ? SPI_DORD_MSK : 0);        \
} while(0)
 
#define spi_destroy(void)                                                    \
do {                                                                         \
    /* Disable the SPI interface */                                          \
    SPCTL = 0;                                                               \
    /* Clear the SPIF and WCOL flags */                                      \
    bit_set(SPSTAT, SPI_SPSTAT_CLEAR_MSK);                                   \
} while(0)
 
 
 
#define spi_set_pin_group(group)                                             \
do {                                                                         \
    bit_clr(P_SW1, SPI_SW_MASK);                                              \
    bit_set(P_SW1, (uint8_t)((group) << SPI_S0_BIT));                        \
} while(0)
 
#define spi_get_pin_group() ((spi_pin_group_t)(bit_shift_right(get_reg(P_SW1, (SPI_S0_MASK | SPI_S1_MASK)), SPI_S0_BIT)))
 
 
 
#define spi_ss_clr(group) spi_ss_clr_##group()
 
#define spi_ss_set(group) spi_ss_set_##group()
 
 
 
#define spi_write_sync(data)                                                 \
do {                                                                         \
    /* Clear the SPIF and WCOL flags */                                      \
    bit_set(SPSTAT, SPI_SPSTAT_CLEAR_MSK);                                   \
    /* Writing the data register starts the transfer */                      \
    SPDAT = (data);                                                          \
    /* Wait until the transfer is finished */                                \
    while (test_if_bit_cleared(SPSTAT, SPI_SPIF_MSK));                       \
    /* Clear the SPIF and WCOL flags */                                      \
    bit_set(SPSTAT, SPI_SPSTAT_CLEAR_MSK);                                   \
} while(0)
 
#define spi_transfer_sync(value, data)                                       \
do {                                                                         \
    spi_write_sync(data);                                                    \
    /* Store the received byte */                                            \
    *(value) = SPDAT;                                                        \
} while(0)
 
 
 
#define spi_async_transfer_start(data)                                       \
do {                                                                         \
    /* Clear the SPIF and WCOL flags */                                      \
    bit_set(SPSTAT, SPI_SPSTAT_CLEAR_MSK);                                   \
    /* Writing the data register starts the transfer */                      \
    SPDAT = (data);                                                          \
} while(0)
 
#define is_spi_async_transfer_complete() (test_if_bit_set(SPSTAT, SPI_SPIF_MSK))
 
#define spi_async_transfer_finish() (bit_set(SPSTAT, SPI_SPSTAT_CLEAR_MSK))
 
#define spi_async_get_result() (SPDAT)
 
 
 
#define is_spi_enabled() (test_if_bit_set(SPCTL, SPI_SPEN_MSK))
 
#define is_spi_master() (test_if_bit_set(SPCTL, SPI_MSTR_MSK))
 
#define is_spi_write_collision() (test_if_bit_set(SPSTAT, SPI_WCOL_MSK))
 
#define spi_get_mode() ((spi_mode_t)get_reg(SPCTL, (SPI_CPOL_MSK | SPI_CPHA_MSK)))
 
#define spi_get_clock() ((spi_clock_t)get_reg(SPCTL, SPI_SPR_MSK))
 
 
#endif