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STC15W408AS library 0.12.0
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Macros | |
| #define | T0 P34 |
| T0 pin definition. | |
| #define | INT0 P32 |
| INT0 pin definition. | |
init | |
Counter initializaion functions | |
| #define | counter0_mode2_init() |
| Initialize mode2 for counter0. | |
start/stop | |
Counter0 start/stop functions | |
| #define | counter0_mode2_start(value) |
| Starts Counter 0 in Mode 2 with a specified initial value. | |
| #define | counter0_mode2_stop() |
| Stop counter0. | |
| #define | is_counter0_mode2_started() (TR0 == 1 && (is_counter0_mode2_gate_opened() || INT0 == 1) ) |
| Get counter0 mode2 started status. | |
read/write | |
Counter get and set value functions | |
| #define | counter0_mode2_get_value() (TL0) |
| get counter0 value in mode2 | |
| #define | counter0_mode2_set_value(value) |
| set counter0 value in mode2 | |
config | |
Counter0 pin output and gate config functions | |
| #define | counter0_mode2_enable_P35_output() (bit_set(INT_CLKO, SBIT0)) |
| enable output to P3.5 | |
| #define | counter0_mode2_disable_P35_output() (bit_clr(INT_CLKO, CBIT0)) |
| disable output to P3.5 | |
| #define | is_counter0_mode2_P35_output_enabled() (test_if_bit_set(INT_CLKO, SBIT0)) |
| get pin P3.5 output state to P3.5 | |
| #define | counter0_mode2_open_gate() (bit_clr(TMOD, CBIT3)) |
| Open counter0 gate. | |
| #define | counter0_mode2_close_gate() (bit_set(TMOD, SBIT3)) |
| Close counter0 gate. | |
| #define | is_counter0_mode2_gate_opened() (test_if_bit_cleared(TMOD, SBIT3)) |
| Get gate state. | |
Counter0 mode 2 routines. This module supports general purpose counter0. Timer can work as COUNTER or TIMER.
Counter increments on T0 pin change state.
Counter0 Mode2 is 8-bit autoreloadable counter.
| #define counter0_mode2_close_gate | ( | ) | (bit_set(TMOD, SBIT3)) |
Close counter0 gate.
Closing gate stop counter0.
| #define counter0_mode2_disable_P35_output | ( | ) | (bit_clr(INT_CLKO, CBIT0)) |
disable output to P3.5
Disable pin P.3.5 state changes on counter0 overflow. By default P3.5 output is disabled
| #define counter0_mode2_enable_P35_output | ( | ) | (bit_set(INT_CLKO, SBIT0)) |
enable output to P3.5
Enable pin P.3.5 state changes on counter0 overflow. By default P3.5 output is disabled
| #define counter0_mode2_get_value | ( | ) | (TL0) |
get counter0 value in mode2
| #define counter0_mode2_init | ( | ) |
Initialize mode2 for counter0.
Enable counter0 interrupt and set mode2.
Mode2 is configured as setting TMOD lowest 4 bytes:
| #define counter0_mode2_open_gate | ( | ) | (bit_clr(TMOD, CBIT3)) |
Open counter0 gate.
When gate is opened counter0 will count. By default after init gate is opened. This routine explicitly open the gate.
| #define counter0_mode2_set_value | ( | value | ) |
set counter0 value in mode2
Call this method before counter0 started.
| value | uint8_t counter value to set |
| #define counter0_mode2_start | ( | value | ) |
Starts Counter 0 in Mode 2 with a specified initial value.
Loads the initial 8-bit value into Counter 0 registers and starts the counter.
| value | 8-bit unsigned integer specifying the initial counter count |
| #define counter0_mode2_stop | ( | ) |
Stop counter0.
Stop count T0 pin state changes. Before stop counter0_mode2_start should be called.
| #define is_counter0_mode2_gate_opened | ( | ) | (test_if_bit_cleared(TMOD, SBIT3)) |
Get gate state.
returns bool. True if gate is opened and false if gate is closed
| #define is_counter0_mode2_P35_output_enabled | ( | ) | (test_if_bit_set(INT_CLKO, SBIT0)) |
get pin P3.5 output state to P3.5
| #define is_counter0_mode2_started | ( | ) | (TR0 == 1 && (is_counter0_mode2_gate_opened() || INT0 == 1) ) |
Get counter0 mode2 started status.